1. Field of the Invention
The present invention relates to a code error detecting and correcting apparatus for a system using with an optical disk to record and/or reproduce data.
2. Description of the Related Art
Recently, a data record/reproduce system using an optical disk as a recording medium has been intensively developed. Although an optical disk memory enables the storage of a large amount of data compared with a magnetic disk, the error ratio of the recording media itself is inherently higher. This disadvantage therefore is covered by adding an error detecting and correcting code to the data, both the data and the error correcting and detecting code should be recorded, on the optical disk. Furthermore, a common method of reproduction detects and corrects an error of data by use of the error detecting and correcting code. FIG. 6 is a schematic diagram showing the conventional error detecting and correcting apparatus. The system of FIG. 6 includes a data buffer 501, error detecting circuit 502, an arithmetic circuit 503 to execute an 8-bit exclusive OR logic, an input signal line (8 bits) 504, and an output signal line 505.
The operation of the conventional example will be described with reference to FIG. 6. First, a receive word read from an optical disk which has undergone a demodulation is deinterleaved and thereafter stored via the input signal line 504 into the data buffer 501. At the same time, the receive word is also delivered to the error detecting circuit 502, which effects a calculation for detecting an error, while the receive word is being received or when the input operation thereof is finished, to correct the error. If it is found that a code error exists in the receive word, the number of errors, the positions of the respective errors, and the value of the errors are determined. Thereafter, the receive word is outputted in the symbol-by-symbol fashion from the data buffer 501. In this operation, if it has been detected that a symbol delivered from the data buffer 501 has an error, the code error detecting circuit 502 outputs the value of error to the exclusive OR circuit 503. As a result, the exclusive-ORed result of the symbol delivered from the data buffer 501 and associated with an error and the value of error is outputted to the output signal line 505, thereby executing an error correction. If the encoding operation has been effected in a multiplexed fashion, the output signal line 505 is connected to a data buffer of an error detecting and correcting apparatus disposed at the subsequent stage. Furthermore, there exists also a method in which a DMA transfer of data is achieved from the data buffer 501 to a memory of a computer.
However, according to the configuration described above, in a case where data decoded by the error correcting apparatus is to be processed by the computer, the encoded data must be transferred from the data buffer of the error detecting and correcting apparatus to the memory in the host computer system. In ordinary cases, for the data transfer operation, a DMA transfer is conducted when a sector of data is completely decoded. During the DMA transfer, since the CPU in the host computer is prevented from accessing the memory, the host computer cannot achieve any job processing. Moreover, since at least a buffer of data is transferred from the data buffer of the error detecting and correcting apparatus in the DMA transfer operation, a satisfactory memory area sufficiently large to receive the data of the DMA transfer must be reserved in the computer. Furthermore, if all data of a sector is not used, there arises a problem that an unnecessary transfer time is elapsed and an unused memory area is reserved. In addition, if it is desired to directly access the data buffer of the error detecting and correcting apparatus from the host computer, since the data buffer contains information symbols, check symbols, and control codes such as a CRC at the same time, the address control for a memory access becomes complex; whereas if only the information symbols are to be successively accessed from the computer by use of data memory addresses, there arises a problem that in addition to the data buffer of the code error detecting and correcting apparatus, a separate data buffer must be disposed between the code error detecting and correcting apparatus and the computer.